Here's a Phase Locked Loop (PLL) FM transmitter circuit with high gain amplifier on the final stage. If the unit is to be used with a stereo encoder, the pre-emphasis must be disabled. The audio input network has a potentiometer to set the audio level and jumper selectable pre-emphasis.The PLL FM transmitter uses the standard PLL architecture. The PLL error voltage is summed at the input of the audio buffer, which is implemented by a BC558 transistor. The PLL error voltage enables the RF output frequency to be locked to the frequency of a stable crystal reference oscillator.
The summed PLL error voltage and audio modulation voltage is applied to the VCO by means of a dual varicap diode.
The voltage controlled oscillator (VCO) of the PLL FM Transmitter is based on a novel double-ended architecture operating at half the output frequency. The variable trimmer VC1 sets the centre frequency of the VCO - more of this later. An RF sample is taken from the VCO (still at f/2) to the PLL. The VCO receives its power from a separate zener-stabilised supply rail. The PLL programmable divide chain is implemented by a handful of 74LS logic (74ALS for the first divide), rather than using a synthesiser chip.
Download PLL FM Transmitter User Manual in pdf format : 1 2 3 4 5 6 7 8 9 10 11
The voltage controlled oscillator (VCO) of the PLL FM Transmitter is based on a novel double-ended architecture operating at half the output frequency. The variable trimmer VC1 sets the centre frequency of the VCO - more of this later. An RF sample is taken from the VCO (still at f/2) to the PLL. The VCO receives its power from a separate zener-stabilised supply rail. The PLL programmable divide chain is implemented by a handful of 74LS logic (74ALS for the first divide), rather than using a synthesiser chip.
Download PLL FM Transmitter User Manual in pdf format : 1 2 3 4 5 6 7 8 9 10 11
Posts
No comments:
Post a Comment